The present invention relates to a power semiconductor device, and more particularly to a power semiconductor device having an insulated gate field effect transistor and a bipolar transistor.
In recent years, power semiconductor devices having advantages to be easily driven and to be able to handle a large current, i.e., power semiconductor devices equipped with the features of both an insulated gate field effect transistor and a bipolar transistor, have been used as power semiconductor devices used for inverters and the like.
As one of the above power semiconductor devices, FIGS. 10(a) and 10(b) show an equivalent circuit of a semiconductor device which is disclosed in U.S. application Ser. No. 08/096,978 filed by the same inventors as the present application. This semiconductor device has major portions that are shown in a cross-sectional view in FIG. 9, and is formed as shown in FIGS. 8(a) to 8(d) and FIG. 9. Namely, as shown in FIG. 8(a), a semiconductor substrate in which an n.sup.- -type layer 3 is epitaxially grown on a p.sup.+ -type layer 2 is prepared. Subsequently, to reduce resistance in a p-type layer 4b serving as a base layer of second and third bipolar transistors (hereafter referred to as Q4 and Q5) which are formed later, a p.sup.+ -type diffused layer 41 is formed in a region where the p-type layer 4b is to be formed, down to a depth which reaches a vicinity of an interface between the p-type layer 4b and the n.sup.- -type layer 3 by selectively injecting boron from the surface of the n.sup.- -type layer 3 and by allowing thermal diffusion to take place.
Then, as shown in FIG. 8(b), after an insulating film and a gate electrode (polysilcon film) are formed one on top of the other, the gate electrode is subjected to patterning, thereby forming first and second electrodes 10 and 11 serving as gate electrodes G1 and G2 of first and second insulated gate field effect transistors (hereafter referred to as Q1 and Q2) on the insulating film. Subsequently, by using the first and second electrodes 10 and 11 as masks, the insulating film is subjected to etching, thereby forming gate oxide films 9a and 9b beneath the first and second electrodes 10 and 11, respectively. At this time, the first and second electrodes 10 and 11 are formed in such a manner that semiconductor regions below the first and second electrodes 10 and 11 and ends which cross the surfaces of the p.sup.+ -type high-concentration layer 41 and a p.sup.+ -type diffused layer 42 do not overlap with each other, respectively. This is because if the concentration at surface portions of a channel layer located immediately below the gate electrodes constituted by the first and second electrodes 10 and 11 is too high, threshold values of MOS 12 or MOS 13 rise, which is not desirable.
Subsequently, by using the first and second electrodes 10 and 11 as masks, boron is injected selectively into the surface of the n.sup.- -type layer 3 and is allowed to diffuse, thereby forming the p-type layer 4b. At this time, in the n.sup.- -type layer 3 below the ends of the first and second electrodes, the p-type layer 4b extends by a predetermined distance below the first and second electrodes 10 and 11 by means of lateral diffusion. In the portion of the n.sup.- -type layer 3 located below the second electrode 11, since the width of the second electrode 11 is small, the p-type layers 4b extending from both ends of the second electrode 11 become connected to each other, so that this entire portion becomes the p-type.
Next, in order to further reduce the resistance at the p-type layer 4b and obtain satisfactory ohmic contact with the electrodes, the p.sup.+ -type layer 42 is formed as shown in FIG. 8(c). As for its procedure, in the same way as the formation of the p.sup.+ -type layer 41, boron is injected selectively into the surface of the n.sup.- -type layer 3 and is allowed to diffuse, thereby forming the p.sup.+ -type diffused layer 42 in substantially the same planar region as the p.sup.+ -type diffused layer 41 so as to be provided with a depth smaller than the depth of the p.sup.+ -type diffused layer 41.
Next, as shown in FIG. 8(d), by using as masks the first and second electrodes 10 and 11 and resist films (not shown) formed selectively in the vicinities of central portions of the surface areas of the p.sup.+ -type diffused layer 41 and the p.sup.+ -type diffused layer 42, arsenic or phosphorus is vapor-phase diffused or ion injected and is allowed to diffuse or recrystallize, thereby forming n.sup.+ -type layers 5a, 6, and 5b. At this time, in a portion of the p-type layer 4b which is located below an end of the first electrode 10, the n.sup.+ -type layer 5a enters slightly below the first electrode 10 by means of lateral diffusion. As a result, a portion of the p-type layer 4b which is located below the first electrode 10 and extends from the end of the n.sup.+ -type layer 5a to the n.sup.- -type layer 3 becomes a channel forming layer. At the ends of the second electrode 11, the n.sup.+ -type layers 6 and 5b enter slightly below the second electrode 11 from the both ends. As a result, a portion of the p-type layer 4b which is located below the second electrode 11 and sandwiched between the n.sup.+ -type layers 6 and 5b becomes a channel forming layer.
Subsequently, as shown in FIG. 9, the first and second electrodes 10 and 11 are insulated by an insulating film, thereby forming third and fourth electrodes 7a and 7b respectively connected to the n.sup.+ -type layers 5a and 5b as well as a fifth electrode 8 for shortcircuiting the n.sup.+ -type layer 6 and the p-type layer 42. Then, a sixth electrode 1 is formed on the other surface of a p.sup.+ -type layer 2.
The relationships between the thus fabricated semiconductor device shown in FIG. 9 and portions of the equivalent circuit shown in FIG. 10 are as follows: Namely, the p.sup.+ -type layer 2 becomes an emitter layer of a first bipolar transistor (hereafter referred to as Q3), and the sixth electrode 1 becomes a collector electrode 1 in the overall semiconductor device. In addition, the first n.sup.- -type layer 3 becomes a first source/drain region layer (hereafter referred to as the S/D region layer) of Q1, a base layer of Q3, and a collector layer of Q4 and Q5. The p-type layer 4b becomes a back gate of Q1 and Q2, a collector layer of Q3, and a base layer of Q4 and Q5.
Furthermore, the n.sup.+ -type layer 5a becomes a second S/D region layer of Q1 and an emitter layer of Q4; the n.sup.+ -type layer 6 becomes a first S/D region layer of Q2; and the n.sup.+ -type layer 5b becomes a second S/D region layer of Q2 and an emitter layer of Q5.
In addition, the first electrode 10 and the second electrode 11 become gate electrodes of Q1 and Q2, respectively; the third electrode 7a serves as both a second source/drain electrode (hereafter referred to as the S/D electrode) of Q1 and an emitter electrode of Q4; and the fourth electrode 7b serves as both a second S/D electrode of Q2 and an emitter electrode of Q5.
In particular, in the above-described semiconductor device, since the p.sup.+ -type diffused layer 41 is formed to reduce resistance R.sub.B2 at the base layer of Q4 and Q5, in particular, it is possible to improve an upper-limit current (a controllable current) where a latch-up of a parasitic thyristor occurs.
Next, referring to FIGS. 9 and 10(a) and 10(b), the operation of the semiconductor device fabricated in the above-described manner will be described.
(1) When the transistor operation is performed, as shown in FIG. 10(a), a positive potential is applied to both the gate electrode (G1) 10 of Q1 and the gate electrode (G2) 11 of Q2 with respect to a common terminal E connected to the second S/D region layer 5a of the n-channel MOS transistor Q1, the second S/D region layer 6 of the n-channel MOS transistor Q2, the emitter electrode 7a of the npn bipolar transistor Q4, and the emitter electrode 7b of the npn bipolar transistor Q5.
Consequently, Q1 and Q2 are turned on. When Q1 is turned on, electrons flow from the first S/D electrode 7a to the second S/D region layer (the emitter layer of Q4) 5a, pass through the channel layer of Q1, and flow into the first S/D region layer (the base layer of Q4) 3. At the same time, the potential at the first S/D region layer (the base layer of Q4) declines. As a result, the pnp bipolar transistor Q3 comprised of the p-type layer (the collector layer of Q3) 4b, the n.sup.- -type layer (the base layer of Q3) 3, and the p.sup.+ -type layer (emitter layer) 2 is turned on.
Then, a hole current passes through the emitter layer 2 of Q3, the base layer 3 of Q3, and the collector layer of Q3, and is drawn to the shortcircuiting electrode 8. Here, a current carrier shifts from holes to electrons, and an electron current flows into the first S/D region layer 6, passes through the channel layer of the already turned-on Q2 and the emitter layer 5b, and is drawn to the emitter electrode 7b.
(2) Next, when the thyristor operation is performed, as shown in FIG. 10(b), a positive potential is applied to the gate electrode (G1) 10 of Q1 with respect to the common terminal E connected to the second S/D region layer 5a of Q1, the second S/D region layer 6 of Q2, the emitter electrode 7a of Q4, and the emitter electrode 7b of Q5.
Consequently, Q1 is turned on. When Q1 is turned on, electrons flow from the first S/D electrode 7a to the second S/D region layer 5a, pass through the channel layer of Q1, and flow into the first S/D region layer (the base layer of Q3) 3. At the same time, the potential at the first S/D region layer (the base layer of Q3) declines. As a result, Q3 is turned on.
Then, holes pass from the emitter layer 2 and the base layer 3 of Q3 and are drawn to the collector layer (the base layer of Q4 and Q5) 4b, so that the potential at the base layer 4b of Q4 and Q5 becomes high. Here, since Q2 is not turned on, the holes are drawn from the base layer 4b of Q4 and Q5 to the emitter layers 7a and 7b of Q4 and Q5. As a result, Q4 and Q5 are turned on, and Q3 and Q4, as well as Q3 and Q5, operate as pairs, respectively, and the thyristor operation begins.
(3) When a shift is made from the above-described thyristor operation to the transistor operation, a high voltage is applied to the gate electrode (G2) of Q2 with respect to the terminal E with the voltage being applied to the gate electrode (G1) of Q1 and in a state in which Q1 is held in the on state, thereby turning on Q2. Consequently, holes are drawn from the base layer 4b of Q4 and Q5, electrons are introduced into the base 4b, and the potential at the base layer 4b of Q4 and Q5 declines, with the result that Q4 and Q5 are turned off. Accordingly, only Q1 and Q2 remain on, and the operation shifts to the transistor operation. It should be noted that, in this case, it is necessary to draw holes from the base of Q4 and Q5 via Q2 and to introduce the electrons into the base layer 4b. The switching speed is determined by that speed.
In the above-described operating state (1), since the emitter electrodes 7a and 7b are shortcircuited, the on voltage of the semiconductor device is expressed mainly as the sum of a junction voltage at a pn junction between the emitter layer 2 and the base layer 3 of Q3, an on voltage between the drain and source of Q1, and a voltage drop in the base layer 3. Meanwhile, a voltage which is equal to the sum of a voltage drop due to the composite resistance R.sub.B2 in the base layer 4b and an on voltage between the drain and source of Q2 occurs between the base and the emitter of each of Q4 and Q5, both of which are thyristor-coupled to Q3. Here, the composite resistance R.sub.B2 occurs within the base layer 4b, i.e., in a region layer extending from a portion below the channel layer of Q1 to a portion below the emitter layer 5a, and to a region layer which is surrounded by the emitter layer 5a and the first S/D region layer 6 and in which a main hole current flows.
Now, if a forward voltage of, for instance, 0.6 V or more, is applied between the base and the emitter of Q4 or Q5, Q4 or Q5 is turned on, so that the operation shifts to the thyristor operation with respect to Q3 and is set in a state which cannot be controlled by the gate. This is called a latch-up phenomenon.
Therefore, the p.sup.+ -type diffused layer 41 and the p.sup.+ -type diffused layer 42 are provided in the above-described semiconductor device in order to reduce R.sub.B2 at the principal channel of the hole current so as to decrease the voltage applied between the base and the emitter of Q4 or Q5 for preventing the occurrence of the latch-up.
This is a method which is taken because the on voltage of Q1 and the on voltage of Q2 are in a relationship of tradeoff, and the concentration in the base layer 4b cannot be made very high in order to optimize a pn junction between the p-type base layer 4b and the n.sup.- -type base layer 3.
In accordance with the above-described comparison example, the principal hole current during the transistor operation passes in the base layer 4b of Q4, specifically from a portion below the region constituting the channel layer of Q1 to the p.sup.+ -type diffused layer 42 via a portion below the emitter layer 5a of Q4 and the p.sup.+ -type diffused layer 41, and is drawn to the shortcircuiting electrode 8. However, since the base layer 4b, the p.sup.+ -type diffused layer 41 and the p.sup.+ -type diffused layer 42 are all formed by the ion injection process, their concentrations are higher toward the surface, so that equivalent resistance is lower toward the surface, and the hole current flows in a portion close to the surface in a concentrated manner. This state is shown in FIG. 6(b) based on computer simulation by using an IGBT (conductivity-modulated transistor) as an example. As a result of the concentration of the current in this manner, as shown in an output characteristic diagram shown in FIG. 7, the collector current Ic is latched up at about 3000 A/cm.sup.2. For this reason, a large main current value cannot be obtained during the transistor operation, so that there is a problem in that the above-described semiconductor device cannot be used for applications for which a greater current is required.
In addition, it takes time to draw the current carrier due to the concentration of the current, so that there is a problem in that the switching speed from the thyristor operation to the transistor operation is delayed.